High Speed Systolic Array Structure for Variable Block Size Motion Estimation

New systolic array based architecture for variable block size motion estimation is presented in this paper. The proposed architecture is scalable for various block sizes. High speed systolic array is designed for Sum of absolute difference (SAD) calculation of 4x4 block sizes. High speed is achieved by group 4 pixels into a single large pixel as sad’s can be calculated simultaneously for all the pixels in a block. Variable block size Sad’s for an 8x8 block is achieved by operating four Systolic arrays in parallel. An Efficient row adder tree is designed to generate Sad’s for 4x8, 8x4, 8x8 block sizes by reusing the 4x4 Sad’s from the outputs of the systolic array. The presented architecture also reduces the data bandwidth by reusing the pixels efficiently without the need for reading the same pixels twice from the search window. VLSI Implementation of Systolic array resulted in a clock frequency of 500 MHz, synthesized using synopsys design compiler targeting 90nm LSI Standard cell library.